AMD shows off stacked 3D V-Cache chiplets, resulting in up to 192MB of L3 cache - Technology News, Mobile Technology News, Videos, and Review | Techbrinks

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Tuesday, 1 June 2021

AMD shows off stacked 3D V-Cache chiplets, resulting in up to 192MB of L3 cache


Developed in collaboration with TSMC, AMD’s first application of the 3D chiplet tech is a vertical cache addition for its high-end processors. In a nutshell, AMD used a process called through-silicon vias (TSVs) to stack additional L3 cache on top of the compute chiplets.

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